Inductor for a system-on-a-chip and method for manufacturing the same

ABSTRACT

An inductor for a system-on-a-chip and a method for manufacturing the inductor are disclosed. The inductor comprises a conductive line formed by connecting a plurality of conductive patterns grown from a seed layer formed on a lower wiring. The method comprises using an electrolytic plating process or an electroless plating process to grow the plurality of adjacent conductive patterns from the seed layer until they become connected. The method also enables adjusting the height and width of the conductive line to desired levels.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to an inductor and a method formanufacturing the inductor. More particularly, the present inventionrelates to an inductor for radio frequency (RF) devices for asystem-on-a-chip (SOC), and a method for manufacturing the inductor.

A claim of priority is made to Korean Patent Application No. 2003-78195filed on Nov. 6, 2003, the disclosure of which is incorporated herein byreference in its entirety.

2. Description of the Related Art

An SOC comprises a single microchip integrating together all of theelements of a system. The elements of the system generally compriseindependently operating semiconductor devices or circuits. For example,an SOC for wireless communications typically includes a microprocessor,a digital signal processor (DSP), a random access memory (RAM) device,and a read only memory (ROM). Generally, the elements of an SOC areintegrated on a large scale integrated (LSI) circuit or an integratedcircuit (IC).

In an SOC for RF communication, semiconductor devices and RF circuitsare generally integrated on a single chip. Inductors are typicallyformed on integrated circuits of the SOC after the integrated circuitsare formed on a semiconductor substrate. A thin film type inductorhaving a spiral or solenoid construction is commonly employed in an SOCbecause it is easily combined with integrated circuits. In addition,thin film type inductors are employed for various devices such as avoltage controlled oscillator (VCO), a filter, or a converter.

A conventional thin film type inductor is disclosed in variousinternational patent publications, including, for example, Korean LaidOpen Patent Publication No. 2003-20,603, Korean Patent No. 348,250, andJapanese Laid Open Patent Publication No. 1998-241,983.

FIGS. 1A to 1C are cross-sectional views illustrating a method ofmanufacturing a conventional inductor disclosed in the above-mentionedKorean Laid Open Patent Publication.

Referring to FIG. 1A, a soft magnetic thin film 15 is formed on asubstrate 10 formed on a silicon wafer. Soft magnetic thin film 15 has adouble-layer structure comprising an iron-tantalum nitride (FeTaN) layerand a titanium (Ti) layer.

An insulation film 20 of silicon oxide is formed on soft magnetic thinfilm 15 and a seed layer 25 for an electroplating process is formed oninsulation film 20. Seed layer 25 has a double-layer structurecomprising a copper (Cu) layer and a chromium (Cr) layer.

A photosensitive film 30 is deposited on the seed layer 25, and then amask 35 is formed over the photosensitive film 30. The photosensitivefilm 30 is exposed through a pattern in mask 35. The pattern of the mask35 defines an inductor having a coil structure.

Referring to FIG. 1B, a plurality of holes are formed through thephotosensitive film 30 by developing the exposed portions of thephotosensitive film 30. The holes expose the seed layer 25 which ispositioned beneath the photosensitive film 30. A coil 40 of the inductoris formed from the seed layer 25 to fill the holes. The coil 40 isformed by an electroplating process using a plating solution includingcopper.

Referring to FIG. 1C, the photosensitive film 30 is removed and portionsof the seed layer 25 exposed between the loops of the coil 40 are etchedaway using a wet etching process to complete the coil 40 on insulationfilm 20. The coil 40 is attached to an upper magnetic film 50 using anadhesive film 45 of epoxy resin to form the inductor on the substrate10.

In the above-described method for manufacturing a conventional inductor,the rate at which the coil 40 grows from the seed layer 25 to fill theholes in the photosensitive film 30 decreases significantly as the sizeof the holes increases. As the width and height of the inductorincrease, the rate of coil growth slows accordingly, thus driving up thetime and cost of manufacturing for the inductor and the related RFdevice. However, it is important for the inductor to have sufficientwidth and height to ensure the desired electrical characteristics of theinductor.

SUMMARY OF THE INVENTION

The present invention provides an inductor for an SOC manufacturedaccording to a simplified process. The present invention also provides alow-cost method for manufacturing an inductor for an SOC using asimplified process.

According to one aspect of the present invention, an inductor comprisesa seed layer formed on a substrate and a conductive line formed on theseed layer. The conductive line is formed by connecting a plurality ofconductive patterns grown from the seed layer. A diffusion preventionlayer is preferably formed between the substrate and the seed layer, anda protection layer is preferably formed on the conductive line.Additionally, a mold layer including hole arrays is preferably filledwith the respective conductive patterns.

According to another aspect of the present invention, an inductorcomprises a substrate including a conductive structure, a seed layerformed on the substrate, a mold layer formed on the seed layer, and aconductive line formed on the seed layer. The mold layer includes holearrays exposing the seed layer, and the conductive line is electricallyconnected to the conductive structure. The conductive line is formed byconnecting a plurality of conductive patterns grown from the seed layer.A protection layer is preferably formed on the conductive line.

According to still another aspect of the present invention, an inductorcomprises a substrate including a conductive structure, a mold layerincluding hole arrays having inner surfaces formed on the substrate, aseed layer formed on the inner surfaces of the hole arrays, and aconductive line formed on the seed layer. The conductive line iselectrically connected to the conductive structure and is formed byconnecting a plurality of conductive patterns grown from the seed layer.

According to still another aspect of the present invention, an inductorcomprises a substrate having a conductive structure, a mold layerincluding hole arrays having inner surfaces formed on the substrate, afirst seed layer formed on the inner surfaces of the hole arrays and onthe mold layer, a capping layer formed on the first seed layer, a secondseed layer formed on portions of the capping layer positioned in thehole arrays, and a conductive line formed on the second seed layer. Theconductive line is electrically connected to the conductive structureand is formed by connecting a plurality of conductive patterns grownfrom the second seed layer.

According to still another aspect of the present invention, there isprovided a method for manufacturing an inductor. The method comprisesforming a mold layer on a seed layer, wherein the mold layer includeshole arrays exposing the seed layer. The method further comprisesforming conductive patterns on the mold layer from the seed layer tofill the hole arrays. The method further comprises forming a conductiveline on the mold layer by growing the conductive patterns on the moldlayer and connecting the conductive patterns. Preferably, the methodfurther comprises forming an anti-reflective layer on the mold layer andforming a protection layer on the conductive line.

According to still another aspect of the present invention, there isprovided a method for manufacturing an inductor. The method comprisesforming a mold layer including hole arrays having inner surfaces on asubstrate including a conductive structure and forming a diffusionprevention layer on the inner surfaces of the hole arrays and on themold layer. The method further comprises forming seed layer patterns onportions of the diffusion prevention layer positioned in the hole arraysand forming conductive patterns from the seed layer patterns to fill thehole arrays. The method also further comprises forming a conductive lineon the mold layer by growing the conductive patterns on the mold layerand by connecting the conductive patterns and forming a protection layeron the conductive line.

According to still another aspect of the present invention, there isprovided a method for manufacturing an inductor. The method comprisesforming a mold layer including hole arrays on a substrate including aconductive structure and forming a diffusion prevention layer on theinner surfaces of the hole arrays and on the mold layer. The methodfurther comprises forming a first seed layer on the diffusion preventionlayer, forming a capping layer on the first seed layer, and formingsecond seed layer patterns on portions of the capping layer positionedin the hole arrays. The method further comprises forming conductivepatterns from the second seed layer patterns to fill the hole arrays,growing the conductive patterns on the mold layer and connecting theconductive patterns, thereby forming a conductive line on the moldlayer, and forming a protection layer on the conductive line.

According to the present invention, an inductor including spiralconductive lines may be readily manufactured at relatively low cost byemploying an electrolytic process or an electroless plating process. Thewidth and height of the conductive lines are adjusted to desired valuesby adjusting the growth rate of the conductive patterns using theelectrolytic plating process or the electroless plating process. Thedesired height of the conductive lines is often relatively high comparedto the height of a conventional inductor. Adjusting the height of theconductive lines permits the inductor formed by the present invention tohave a relatively high spiral structure on the substrate.

The manufacturing time and cost associated with forming the inductor arepotentially reduced by a significant margin because an additionalprocess for electrically connecting the inductor to a lower wiringstructure formed on the substrate is not required. Accordingly, theinductor is preferably formed directly on a conventional substratewithout any additional process so that an inductor having a relativelyhigh spiral structure is readily formed on the substrate at low costusing a conventional apparatus for manufacturing the inductor.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings illustrate several selected embodiments of thepresent invention. In the drawings:

FIGS. 1A to 1C are cross-sectional views illustrating a method formanufacturing a conventional inductor;

FIG. 2 is a planar view illustrating an exemplary inductor formed inaccordance with one aspect of the present invention;

FIGS. 3A to 3E are cross-sectional views of the inductor shown in FIG. 2taken along the line from I to I′ in FIG. 2.

FIGS. 3A to 3E illustrate a method for manufacturing the inductor shownin FIG. 2;

FIG. 4A is a planar view further illustrating the mask element shown inFIG. 3B;

FIG. 4B is a planar view further illustrating a mask for formingconductive patterns according to one aspect of the present invention;

FIG. 5A is an electron micrograph image illustrating cross-sections ofthe conductive patterns in FIG. 3C;

FIG. 5B is an electron micrograph image illustrating a planar view ofthe inductor in FIG. 3E;

FIG. 6 is a cross-sectional view illustrating an exemplary inductoraccording to another aspect of the present invention;

FIGS. 7A to 7E are cross-sectional views illustrating a method formanufacturing the exemplary inductor in FIG. 6;

FIG. 8 is an electron micrograph image illustrating cross-sections ofconductive patterns in FIG. 7C;

FIGS. 9A to 9E are cross-sectional views illustrating a method formanufacturing an inductor according to yet another aspect of the presentinvention;

FIGS. 10A and 10B are electron micrograph images illustratingcross-sections of conductive patterns in FIG. 9D;

FIG. 11 is a planar view illustrating an exemplary inductor according tostill another aspect of the present invention;

FIG. 12 is a cross-sectional view illustrating a section of the inductorshown in FIG. 11 taken along the line from II to II′; and,

FIGS. 13A to 13D are cross-sectional views illustrating a method formanufacturing the inductor in FIG. 12.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described more fully with reference tothe accompanying drawings, in which several embodiments of the presentinvention are shown. In the drawings, the thickness of layers andregions are exaggerated for clarity and like reference numerals refer tolike elements throughout. It will be understood that when an elementsuch as a layer, region or substrate is referred to as being “on” or“onto” another element, the layer is either directly on the otherelement or intervening elements may also be present.

FIG. 2 is a planar view illustrating an inductor according to one aspectof the present invention. In FIG. 2, an inductor 200 includes a spiralconductive line 190. The spiral conductive line 190 is electricallyconnected to a contact 160 formed as a part of a lower wiring elementformed on a substrate. Thus, the spiral conductive line 190 ispositioned over the lower wiring including the contact 160 and formed ina spiral structure. The conductive line 190 is preferably formed byconnecting a plurality of conductive patterns grown from a seed layer(not shown).

The inductor 200 typically includes the seed layer formed over thesubstrate. A multi-layer structure including an insulating interlayer ora conductive layer is typically formed between the substrate and theseed layer.

FIGS. 3A to 3E are cross-sectional views taken along a line extendingfrom I to I′ in FIG. 2. FIGS. 3A to 3E illustrate a method formanufacturing the inductor of FIG. 2.

Referring to FIG. 3A, an insulation layer 150 is formed on a substrate(not shown) including a lower conductive structure. An opening 155 isformed through the insulation layer 150 by partially etching theinsulation layer 150 using a photolithography process. The lowerconductive structure typically includes a word line, a bit line, aconductive pattern, and a pad. The opening 155 exposes a portion of alower wiring (not shown) electrically connected to the lower conductivestructure.

A conductive layer is formed on insulation layer 150 to fill the opening155. The conductive layer is typically formed using conductive materialsuch as metal or polysilicon doped with impurities. The conductive layeris partially removed by a chemical mechanical polishing (CMP) process,an etch back process, a combination of a CMP process and an etch backprocess, or a photolithography process, until the insulation layer 150is exposed. As a result of partially removing the conductive layer, acontact 160 electrically connected to the lower wiring is formed in theopening 155. The lower wiring including the contact 160 is electricallyconnected to the lower conductive structure positioned on the substrate.

A diffusion prevention layer 165 is formed on the contact 160 and theinsulation layer 150. The diffusion prevention layer 165 typically has asingle-layer structure or a multi-layer structure. The single layerstructure typically uses tantalum (Ta), tantalum nitride (TaN),tantalum-aluminum nitride (TaAlN), tantalum silicide (TaSi₂), titanium(Ti), titanium nitride (TiN), titanium-silicon nitride (TiSiN), ortungsten nitride (WN). The multi-layer structure typically uses amixture including at least two elements from the group consisting oftantalum (Ta), tantalum nitride (TaN), tantalum-aluminum nitride(TaAlN), tantalum silicide (TaSi₂), titanium (Ti), titanium nitride(TiN), titanium-silicon nitride (TiSiN), and tungsten nitride (WN). Thediffusion prevention layer 165 typically has a thickness of about 50 to1,000 Å. The diffusion prevention layer 165 prevents copper included ina conductive pattern 185 (see FIG. 3C) from diffusing into theunderlying structure.

A seed layer 170 is formed on the diffusion prevention layer 165. Theseed layer 170 is typically formed by a chemical vapor deposition (CVD)process or a physical vapor deposition (PVD) process such as asputtering process or a vacuum evaporation process. Preferably, the seedlayer 170 is formed by a PVD process and has a thickness of about 100 to5,000 Å. Alternatively, the seed layer 170 is formed using a conductivematerial that substantially prevents formation of a surface insulationfilm such as an oxide film or a nitride film. For example, the seedlayer 170 is formed using platinum (Pt), palladium (Pd), nickel (Ni),silver (Ag), gold (Au) or an alloy thereof.

A photoresist film is coated on the seed layer 170. The photoresist filmis exposed to light through a mask 220 having a plurality of holes asshown in FIG. 3B. The photoresist film serves as a mold layer forforming the conductive line 190, as shown in FIG. 3D. The photoresistfilm typically has a thickness of about 500 to 30,000 Å so as tosufficiently grow conductive patterns 185 (See, FIG. 3C).

FIG. 4A is a planar view further illustrating the mask 220 in FIG. 3B.

Referring to FIGS. 3B and 4A, the mask 220 includes a pattern 215 havinga plurality of hole arrays arranged in a spiral shape so as to form theinductor 200 having the conductive lines 190. When the photoresist filmis exposed using the mask 220, the photoresist film forms a plurality ofhole arrays in the spiral shape of the mask 220. After the exposedphotoresist film is developed, a photoresist pattern 175 including aplurality of trenches or hole arrays 180 arranged in the spiral shape ofthe mask 220 is formed on the seed layer 170.

Although FIG. 4 shows a pair of spiral-shaped hole arrays formed in themask 220, the number and size of the hole arrays is variable, and itchanges in accordance with the size and structure of the inductor 200.

FIG. 4B is a planar view illustrating a mask 230 for forming aconductive line according to one particular embodiment of the presentinvention.

Referring to FIG. 4B, mask 230 includes a pattern 225 having a pluralityof trenches spirally arranged according to a structure of an inductor.The size and number of trenches varies according to the size andstructure of the inductor.

Referring now to FIG. 3B, the photoresist film is exposed and developedusing mask 220 and as a result, a photoresist pattern 175 having holearrays 180 is formed on seed layer 170. Trenches or hole arrays 180partially expose seed layer 170. Trenches or hole arrays 180 preferablyhave a depth of about 500 to 30,000 Å.

According to one aspect of the present invention an anti-reflectivelayer (ARL) is formed on the photoresist film so as to ensure a processmargin in a photolithography process. The photoresist pattern 175 isthen formed on the seed layer 170 by patterning the photoresist filmusing the ARL as an etching mask. The ARL typically has a thickness ofabout 50 to 1,000 Å.

In another aspect of the present invention, an etch-stop layer is formedon the seed layer 170 in consideration of a successive etching process.The photoresist pattern 175 is then formed on the etch-stop layer. Theetch-stop layer is typically formed using nitride such as siliconnitride.

Referring to FIG. 3C, a plurality of conductive patterns 185 is formedon the photoresist pattern 175 from the seed layer 170 by anelectrolytic plating process to fill trenches or hole arrays 180. Theelectrolytic plating process is typically performed with a currentdensity of about 20 to 40 mA/cm² using a plating solution including acopper sulfate (CuSO₄) solution, a sulfuric acid (H₂SO₄) solution, and asolution including chlorine ions (Cl⁻). The conductive patterns 185 aregrown from the seed layer 170 in a direction indicated by arrows in FIG.3C so that upper portions of the conductive patterns 185 are formed onthe photoresist pattern 175. When the conductive patterns 185 are grownin the hole arrays 180 from the seed layer 170, growth within the holearrays 180 accelerates in a vertical direction relative to thesubstrate, whereas the growth within the hole arrays 180 is limitedalong a horizontal direction relative to the substrate. Once theconductive patterns 185 fill the hole arrays 180, upper portions of theconductive patterns 185 form protrusions on the photoresist pattern 175.

Referring to FIG. 3D, the electrolytic plating process used to form theconductive patterns 185 of FIG. 3C is extended to form conductive line190 on the photoresist pattern 175. In other words, the conductivepatterns 185 are vertically and horizontally grown on the photoresistpattern 175 until the conductive patterns 185 become connected to eachother, thus forming the conductive line 190 on the photoresist pattern175. When the conductive line 190 is formed by extending theelectrolytic plating process, an upper portion of the conductive line190 typically has a mushroom shape.

A summary of the process used to form the conductive line 190, includingsome additional details, is now given. The conductive patterns 185 arevertically grown from the seed layer 170. Next, the conductive patterns185 are horizontally and vertically grown on the photoresist pattern 175as shown in FIGS. 3C and 3D. Then, adjacent conductive patterns 185 areconnected to each other on the photoresist pattern 175 according totheir vertical and horizontal growth, resulting in the formation of theconductive line 190. The width and thickness of the conductive line 190are adjusted to desired values by adjusting the vertical and horizontalgrowth of the conductive patterns 185. To achieve this result, theelectrolytic plating process is extensively performed to further growthe conductive patterns 185 once they have already filled the holearrays 180. The further growth causes adjacent conductive patterns 185to become connected to each other, thus forming the conductive line 190on the photoresist pattern 175. In order to form the conductive line 190with the desired width and thickness, the growth of the conductivepatterns 185 is advantageously adjusted after filling the hole arrays180. The conductive line 190 preferably has a thickness of about 1,000to 100,000 Å. The conductive line 190 typically has a sufficientthickness on the photoresist pattern 175 because the horizontal growthof the conductive patterns 185 is limited in the hole arrays 180.

Referring to FIG. 3E, the photoresist pattern 175 is partially removedexcept for a portion of the photoresist pattern 175 positioned beneaththe conductive line 190. When the photoresist pattern 175 is partiallyremoved, the seed layer 170 is partially exposed. The exposed seed layer170 and the diffusion prevention layer 165 are partially removed tocomplete the conductive lines 190 having spiral structures. Thephotoresist pattern 175, the seed layer 170 and the diffusion preventionlayer 165 are partially removed by a wet etching process. The wetetching process is executed using an organic stripper, a solutionincluding ozone (O₃) at a relatively high concentration, or a standardcleaning (SC) solution including carbon dioxide (CO₂). Alternatively,the photoresist pattern 175 may be partially removed by an ashingprocess and/or a stripping process. In one embodiment of the presentinvention, the seed layer 170 and the diffusion prevention layer 165 maybe partially removed using a mixture of a hydrogen fluoride (HF)solution and a hydrogen peroxide (H₂O₂) solution or a mixture of ahydrogen fluoride (HF) solution and a nitric acid (HNO₃) solution. Whenthe ARL is formed on the photoresist pattern 175, the ARL and thephotoresist pattern 175 are simultaneously removed.

A protection layer 195 is formed to enclose the conductive line 190,thereby completing the inductor 200, which preferably comprises aplurality of the conductive lines 190. The inductor 200 has a spiralstructure formed by the plurality of the conductive lines 190. Theprotection layer 195 is typically formed using silicon carbide (SiC) orsilicon nitride (SiN). Alternatively, the protection layer 195 has amulti-layer structure including at least two films of silicon carbide,silicon nitride and silicon oxycarbide. The protection layer 195preferably has a thickness of about 100 to 1,000 Å. The protection layer195 is formed on a sidewall of a remaining portion of the diffusionprevention layer 165, a sidewall of a remaining portion of the seedlayer 170, a sidewall of a remaining portion of the photoresist pattern175, and on the conductive lines 190 of the spiral structure.

FIG. 5A is an electron micrograph image displaying cross sections ofconductive patterns in FIG. 3C. FIG. 5B is an electron micrograph imageshowing a plan view of the inductor in FIG. 3E.

Referring to FIGS. 5A and 5B, the conductive patterns 185 are verticallyand horizontally grown by the above-described electrolytic platingprocess to form the inductor 200 including spiral conductive lines 190on the photoresist pattern 175. Each of the conductive patterns 185 hasan upper portion with a mushroom shape.

FIG. 6 is a cross sectional view illustrating an inductor according toone aspect of the present invention. According to this aspect, a methodfor manufacturing conductive lines comprises processes identical to theprocesses described with reference to FIGS. 3A to 3D.

Referring to FIG. 6, a method for manufacturing an inductor 300 isdescribed. The inductor 300 is manufactured on a substrate having aninsulation layer 250, which has a contact 260 running through it aspreviously described. A photoresist pattern for forming conductive lines290 is completely removed and a seed layer 270 and a diffusionprevention layer 265 are partially removed. Thus, lower portions ofconductive lines 290 are exposed.

A protection layer 295 is formed on the insulation layer 250, onsidewalls of the exposed seed layer 270 and diffusion prevention layer265, and on the conductive lines 290. The protection layer 295 typicallyhas a single-layer structure of silicon carbide, silicon oxycarbide, orsilicon nitride or a multi-layer structure having layers chosen from thegroup consisting of silicon carbide, silicon oxycarbide and siliconnitride. The protection layer 295 is formed from the upper portions ofthe conductive lines 290 to the insulation layer 265 to thereby entirelyenclose the conductive lines 290.

FIGS. 7A to 7E are cross-sectional views illustrating a method ofmanufacturing the inductor in FIG. 6. In FIGS. 7A to 7E, a substrateincluding a lower conductive structure having word lines, bit lines andpads is not shown.

Referring to FIG. 7A, an insulation layer 350 is formed on thesubstrate. The insulation layer 350 is partially etched to form anopening 355 that exposes a lower wiring electrically connected to thelower conductive structure.

A conductive layer is formed on the insulation layer 350 to fill theopening 355. The conductive layer may be formed using metal or dopedpolysilicon. The conductive layer is then partially removed by a CMPprocess, an etch back process or a combination of a CMP process and anetch back process. The conductive layer is partially removed until theinsulation layer 350 is exposed. Thus, a contact 360 electricallyconnected to the lower wiring is formed in the opening 355. The lowerwiring including the contact 360 is electrically connected to the lowerconductive structure formed on the substrate.

A mold layer 365 is formed on the insulation layer 350 and the contact360. The mold layer 365 may be formed using oxide or photoresist. Themold layer 365 is partially etched to form a plurality of trenches orhole arrays 370 that expose the contact 360 as described above. The moldlayer 365 typically has a thickness of about 500 to 30,000 Å so as toeasily form a conductive line 400 (see FIG. 7D) and to sufficientlyisolate the lower conductive structure from the conductive line 400.

When the mold layer 365 is formed using oxide, a photoresist film isadditionally formed on the mold layer 365. The photoresist film isexposed using the mask shown in FIG. 4A or FIG. 4B to form a photoresistpattern including a plurality of hole arrays or trenches. After an ARLhaving a thickness of about 50 to 1,000 Å is additionally formed on thephotoresist film, the photoresist pattern is formed on the mold layer365. Subsequently, the mold layer 365 is etched using the photoresistpattern as an etching mask to thereby form trenches or hole arrays 370having depth of about 500 to 1,000 Å through the mold layer 365.

When the mold layer 365 is formed using photoresist, the mold layer 365is preferably directly exposed using the mask in FIG. 4A or FIG. 4B tothereby form the trenches or hole arrays 370 through the mold layer 365,wherein the trenches or hole arrays 370 have inner surfaces.

Referring to FIG. 7B, a diffusion prevention layer 375 is formed on themold layer 365, on the contact 360, and on the inner surfaces of thetrenches or hole arrays 370. The diffusion prevention layer 375 has athickness of about 50 to 1,000 Å. The diffusion prevention layer 375typically has a single-layer structure or a multi-layer structure. Thesingle-layer structure typically includes tantalum, tantalum nitride,tantalum-aluminum nitride, tantalum-silicon nitride, tantalum silicide,titanium, titanium nitride, tungsten nitride, titanium-silicon nitride,or an alloy thereof. The multi-layer structure typically includes atleast two elements from the group consisting of tantalum, tantalumnitride, tantalum-aluminum nitride, tantalum-silicon nitride, tantalumsilicide, titanium, titanium nitride, tungsten nitride, titanium-siliconnitride, and any alloy thereof.

A first seed layer 380 is formed on diffusion prevention layer 375 by aCVD process or a PVD process such as a sputtering process or a vacuumevaporation process. The first seed layer 380 has a thickness of about100 to 5,000 Å. The first seed layer 380 is preferably formed usingcopper, platinum, palladium, nickel, silver, gold, or an alloy thereof.

A capping layer 385 is formed on the first seed layer 380 using a metalsuch as aluminum. The capping layer 385 has a thickness of about 100 to500 Å. When a portion of a second seed layer 390 on the mold layer 365is removed, a metal oxide film is formed on the capping layer 385 as aresult of oxidation in metal in the capping layer 385. That is, an upperportion of the capping layer 385 except other portion of the cappinglayer 385 formed in the hole arrays 370 is converted into an insulationfilm of metal oxide so that the capping layer 385 may selectivelyrestrain growth of conductive patterns 395. (See, FIG. 7C). Therefore,the conductive patterns 395 may rapidly grow in the hole arrays 370,whereas the conductive patterns 395 may slowly grow on the metal oxidefilm of the capping layer 385. The second seed layer 390 is formed oncapping layer 385 using copper, platinum, palladium, nickel, silver,gold or an alloy thereof.

Referring to FIG. 7C, to perform a selective electrolytic platingprocess, a portion of the second seed layer 390 positioned on the moldlayer 365 is removed by a CMP process, an etch back process or acombination of a CMP process and an etch back process. As a result, thesecond seed layer patterns 393 are formed on the inner surfaces of thehole arrays 370. The diffusion prevention layer 375, the first seedlayer 380, the capping layer 385 and the second seed layer patterns 393are successively formed on the inner surfaces of the hole arrays 370,whereas the second seed layer patterns 393 are not formed on the moldlayer 365.

The conductive patterns 395 selectively and vertically grow from thesecond seed layer patterns 393 to fill the hole arrays 370 using theselective electrolytic plating process. The selective electrolyticplating process is carried out with a current density of about 20 to 40mA/cm² using a plating solution that includes a copper sulfate solution,a sulfuric acid solution, and a solution including chlorine ions. Asdescribed above, since the horizontal growth of the conductive patterns395 is limited in the hole arrays 370, the conductive patterns 395 arevertically grown from the second seed layer patterns 393 in the holearrays 370. When the selective electrolytic plating process iscontinually performed, the conductive patterns 395 filling the holearrays 370 grow horizontally and vertically on the mold layer 365. Thecapping layer 385 including the metal oxide film restrains thehorizontal growth of the conductive patterns 395 in the hole arrays 370.However, because a bottleneck structure is formed at upper portions ofthe hole arrays 370 due to the capping layer 385, the conductivepatterns 395 grow horizontally and vertically after the hole arrays 370are filled with conductive patterns 395. The conductive patterns 395filling the hole arrays 370 continuously grow in horizontal and verticaldirections as indicated by arrows so that adjacent conductive patterns395 become connected to one another to form the conductive line 400having a desired width and height.

FIG. 8 is an electron micrograph image displaying cross-sections ofconductive patterns in FIG. 7C.

As shown in FIGS. 7C and 8, although the horizontal growth of theconductive patterns 395 is restrained in the hole arrays 370, theconductive patterns 395 grow both vertically and horizontally afterfilling hole arrays 370. As a result, adjacent conductive patterns 395become connected to one another, thereby forming a conductive line 400.

Referring to FIG. 7D, the conductive line 400 having a desired width andheight is formed on the mold layer 365 from the second seed layerpatterns 393 by connecting adjacent conductive patterns 395. Theconductive patterns 395 are connected by continuously performing theelectrolytic plating process. After the conductive patterns 395 fill thehole arrays 370, the growth rate of the conductive patterns 395 may beadvantageously adjusted to form the conductive line 400 having a heightof about 1,000 to 100,000 Å.

Referring to FIG. 7E, the capping layer 385, the first seed layer 380and the diffusion prevention layer 375 are partially removed except forportions covered by conductive line 400. A protection layer 405 isformed to cover the conductive line 400, thereby forming an inductor 430having a spiral structure including a plurality of conductive lines 400.The capping layer 385, the first seed layer 380 and the diffusionprevention layer 375 may be partially removed using a mixture of ahydrogen fluoride solution and a hydrogen peroxide solution, or amixture of a hydrogen fluoride solution and a nitric acid solution.

In one embodiment of the present invention, after the mold layer 365 isremoved, the protection layer 405 is formed on the conductive line 400.When the mold layer 365 is formed using photoresist, the mold layer 365is preferably removed using an organic stripper, a solution includingozone at relatively high concentration, or an SC solution includingcarbon dioxide. When the mold layer 365 is formed using oxide, the moldlayer 365 is preferably removed by a wet etching process using asulfuric acid solution or a dry etching process such as a reactive ionetching process or a plasma etching process.

Referring now to FIG. 7E, the protection layer 405 is preferably formedusing silicon carbide or silicon nitride. The protection layer 405 has athickness of about 100 to 1,000 Å. The protection layer 405 enclosesexposed sidewalls of the capping layer 385, the first seed layer 380 andthe diffusion prevention layer 375 beneath the conductive line 400.

In one embodiment of the present invention, the protection layer 405 hasa multi-layer structure including at least elements from the groupconsisting of silicon carbide, silicon nitride and silicon oxycarbide.

FIGS. 9A through 9E are cross-sectional views illustrating a method ofmanufacturing an inductor according to one aspect of the presentinvention.

Referring to FIG. 9A, an insulation layer 450 is formed on a substrateincluding a lower conductive structure. The insulation layer 450 ispreferably formed using oxide or nitride. The insulation layer 450 ispartially etched by a photolithography process and then an opening 455is formed through the insulation layer 450. The lower conductivestructure typically includes word lines, bit lines and pads. The opening455 exposes a lower wiring electrically connected to the lowerconductive structure.

A conductive layer of metal or doped polysilicon is formed on theinsulation layer 450 to fill the opening 455. The conductive layer ispartially removed by a CMP process, an etch back process, or acombination of a CMP process and an etch back process, thereby forming acontact 460 in the opening 455. The contact 460 is electricallyconnected to the lower wiring. Hence, the lower wiring including thecontact 460 is electrically connected to the lower conductive structure.

A mold layer 465 having a thickness of about 500 to 30,000 Å is formedon the insulation layer 450 and the contact 460. The mold layer 465 maybe formed using oxide or photoresist. The mold layer 465 is partiallyetched to form a plurality of trenches or hole arrays 470 exposing thecontact 460 as described above. The trenches or the hole arrays 470 havedepth of about 1,000 to 30,000 Å.

When the mold layer 465 is formed using oxide, a photoresist film isadditionally formed on the mold layer 465. The photoresist film isexposed using one of the masks shown in FIG. 4A and FIG. 4B to form aphotoresist pattern including a plurality of hole arrays or trenches. AnARL having a thickness of about 50 to 1,000 Å is typically also formedon the photoresist film and then the photoresist pattern is formed onthe mold layer 465. Subsequently, the mold layer 465 is etched using thephotoresist pattern as an etching mask to thereby form the trenches orhole arrays 470 through the mold layer 465.

When mold layer 465 is formed using photoresist, the mold layer 465 ispreferably directly exposed using one of the masks in FIG. 4A and FIG.4B without forming an additional photoresist film, thereby forming thetrenches or hole arrays 470 through the mold layer 465, wherein thetrenches or hole arrays 470 have inner surfaces. An additional ARL ispreferably formed on the mold layer 465 to ensure a process margin for aphotolithography process.

Referring to FIG. 9B, a diffusion prevention layer 475 having athickness of about 50 to 1,000 Å is formed on the mold layer 465, onvcontact 460 and on the inner surfaces of the hole arrays 470. Thediffusion prevention layer 475 typically has a single-layer structure ora multi-layer structure. The single-layer structure typically includestantalum, tantalum nitride, tantalum-aluminum nitride, tantalum-siliconnitride, tantalum silicide, titanium, titanium nitride, tungstennitride, titanium-silicon nitride, or an alloy thereof. The multi-layerstructure typically includes at least two elements from the groupconsisting of tantalum, tantalum nitride, tantalum-aluminum nitride,tantalum-silicon nitride, tantalum silicide, titanium, titanium nitride,tungsten nitride, titanium-silicon nitride, and any alloy thereof.

A seed layer 480 having a thickness of about 100 to 5,000 Å is formed onthe diffusion prevention layer 475 by a CVD process or a PVD processsuch as a sputtering process or a vacuum evaporation process. The seedlayer 480 is preferably formed using copper, platinum, palladium,nickel, silver, gold, or an alloy thereof.

Referring to FIG. 9C, seed layer patterns 483 are formed on the contact460 and on the diffusion prevention layer 475 positioned on the innersurfaces of the hole arrays 470 to achieve a selective electrolessplating process. The seed layer patterns 483 are formed by partiallyremoving the seed layer 480 using a CMP process, an etch back process ora combination of a CMP process and an etch back process until thediffusion prevention layer 475 is exposed. As a result, the diffusionprevention layer 475 and the seed layer patterns 483 are positioned onthe inner surfaces of the hole arrays 470, whereas only the diffusionprevention layer 475 is positioned on the mold layer 465.

Referring to FIG. 9D, using the selective electroless plating process,conductive patterns 485 are formed from the seed layer patterns 483 tofill the hole arrays 470. The electroless plating process is carried outusing a copper sulfate solution including a reducing agent such asformaldehyde or hydrazine. As described above, since the horizontalgrowth of the conductive patterns 485 is limited in the hole arrays 470,the conductive patterns 485 are vertically grown from the seed layerpatterns 483 in the hole arrays 470. When the electroless platingprocess is continually performed, the conductive patterns 485 fill thehole arrays 470 and then grow horizontally and vertically on the moldlayer 465. The conductive patterns 485 filling the hole arrays 470continuously grow in the horizontal and vertical directions indicated byarrows so that adjacent conductive patterns 485 become connected to oneanother to form a conductive line 490 having a desired width and height.

FIGS. 10A and 10B are electron micrograph images illustrating crosssections of conductive patterns 485 in FIG. 9D.

Referring to FIGS. 9D, 10A and 10B, as the electroless plating processproceeds, the conductive patterns 485 grow vertically from the seedlayer patterns 483 to fill the hole arrays 470. Then, the conductivepatterns 485 grow vertically and horizontally on the mold layer 465. Inthe present embodiment, the conductive patterns 485 are formed by theelectroless plating process, causing conductive patterns 485 haverelatively dense structures.

Referring to FIG. 9E, the electroless plating process is continuallyperformed to connect adjacent conductive patterns 485 grown from theseed layer patterns 483. The conductive patterns 485 grow continuouslyon the mold layer 465 in vertical and horizontal directions and as aresult adjacent conductive patterns 485 become connected to one anotheron the mold layer 465. As shown in FIGS. 9D, 10A and 10B, after theconductive patterns 485 grow from the seed layer patterns 483 in thevertical direction, they grow on the mold layer 465 in vertical andhorizontal directions. The conductive line 490 is formed by connectingthe conductive patterns 485. The growth rate of the conductive patterns485 is typically adjusted after the conductive patterns 485 fill thehole arrays 470, in order to form the conductive line 490 with a desiredwidth and height.

Referring now to FIG. 9E, a protection layer 495 having a thickness ofabout 100 to 1,000 Å is formed on the mold layer 465 to enclose theconductive line 490. The protection layer 495 may be formed usingsilicon carbide or silicon nitride.

A portion of the protection layer 495 positioned on the mold layer 465is removed to complete the protection layer 495 enclosing the conductiveline 490. As a result, an inductor 500 having spiral conductive lines490 is formed on the substrate.

In one embodiment of the present invention, after the mold layer 465 isremoved, the protection layer 495 is formed to enclose the conductiveline 490. Since the diffusion prevention layer 475 positioned beneaththe conductive line 490 is not removed, a sidewall of the diffusionprotection layer 475 is also enclosed by the protection layer 495.

FIG. 11 is a planar view illustrating an inductor in accordance with oneembodiment of the present invention and FIG. 12 is a cross-sectionalview illustrating a section of the inductor in FIG. 11 taken along theline extending from II to II′.

Referring to FIGS. 11 and 12, an inductor 600 includes a spiralconductive line 590 directly connected to a lower wiring 560 includingpads 570 for input-output of electrical signals. In other words, in theinductor 600, spiral conductive line 590 is directly connected to endportions (pads 570) of the lower wiring 560 without an additionalelectrical contact connecting it to the lower wiring 560. Omitting theadditional electrical contact facilitates a simpler, lower-costmanufacturing processes because it eliminates the need for processesforming the contact.

An opening 515 is formed through a portion of the lower wiring 560 wherethe spiral conductive line 590 passes over it so as to prevent thespiral conductive line 590 from connecting to the lower wiring 560. Thespiral conductive line 590 is directly connected to the end portions(pads 570) of the lower wiring 560, whereas the spiral conductive line590 has no contact with the lower wiring 560 because the opening 515 isformed through the portion of the lower wiring 560.

FIGS. 13A to 13D are cross-sectional views illustrating a method formanufacturing the inductor in FIG. 12.

Referring to FIG. 13A, an insulation layer 550 is formed on a substrateincluding a lower conductive structure. The insulation layer 550 istypically formed using oxide or nitride.

A conductive layer is formed on the insulation layer 550 using metal ordoped polysilicon to form a lower wiring 560 on the insulation layer560. As shown in FIG. 11, the conductive layer is patterned to form thelower wiring 560, which is electrically connected to the lowerconductive structure. An opening 515 having a predetermined width issimultaneously formed through a portion of the lower wiring 560 where aspiral conductive line 590 (see FIG. 13C) passes over it. The opening515 preferably has a width slightly greater than a width of the spiralconductive line 590.

Referring to FIG. 13B, a mold layer 565 having a thickness of about 500to 30,000 Å is formed on the lower wiring 560 to fill the opening 515.The mold layer 565 may be formed using oxide or photoresist. The moldlayer 565 is partially etched to form a plurality of holes thatsimultaneously expose end portions (that is, pads) of the lower wiring560 and a portion of the insulation layer 550 through the opening 515.Each of the holes formed through the mold layer 565 has a depth of about500 to 30,000 Å. As described above, a photoresist film is additionallyformed on the mold layer 565 when the mold layer 565 is formed usingoxide. The photoresist film is exposed using a mask substantiallysimilar to that of FIG. 4A or FIG. 4B to form a photoresist patternincluding a plurality of holes. An ARL having a thickness of about 50 to1,000 Å is typically additionally formed on the photoresist film. Themold layer 565 is then etched using the photoresist pattern as anetching mask to form the holes through the mold layer 565. When the moldlayer 565 is formed using photoresist, the mold layer 565 may bedirectly exposed using a mask substantially similar to that of FIG. 4Aor FIG. 4B without forming an additional photoresist film, therebyforming the holes through the mold layer 565, wherein the holes haveinner surfaces. An additional ARL may be directly formed on the moldlayer 565 to ensure a process margin of a photolithography process.

A diffusion prevention layer 575 having a thickness of about 50 to 1,000Å is formed on the exposed end portions of the lower wiring 560, on theexposed portion of the insulation layer 550, on the inner surfaces ofthe holes, and on the mold layer 565. The diffusion prevention layer 575typically has a single-layer structure or a multi-layer structure. Thesingle-layer structure typically includes tantalum, tantalum nitride,tantalum-aluminum nitride, tantalum-silicon nitride, tantalum silicide,titanium, titanium nitride, tungsten nitride, titanium-silicon nitride,or an alloy thereof. The multi-layer structure typically includes atleast two elements from the group consisting of tantalum, tantalumnitride, tantalum-aluminum nitride, tantalum-silicon nitride, tantalumsilicide, titanium, titanium nitride, tungsten nitride, titanium-siliconnitride, and any alloy thereof.

A seed layer having a thickness of about 100 to 5,000 Å is formed on thediffusion prevention layer 575 by a CVD process or a PVD process. Theseed layer is preferably formed using copper, platinum, palladium,nickel, silver, gold, or an alloy thereof.

To achieve a selective electrolytic or electroless plating process, seedlayer patterns 580 are formed on the inner surfaces of the holes and theend portions of the lower wiring 560 by removing a portion of the seedlayer positioned on mold layer 565. The Seed layer patterns 580 may beformed by a CMP process, an etch back process, or a combination of a CMPprocess and an etch back process. Here, the diffusion prevention layer575, which is positioned on the mold layer 565, is not etched. Hence,the seed layer patterns 580 and the diffusion prevention layer 575 arepositioned on the inner surfaces of the holes, whereas only thediffusion prevention layer 575 is positioned on the mold layer 565.

Conductive patterns 585 are formed from the seed layer patterns 580 tofill the holes by a selective electrolytic or electroless platingprocess. The selective electrolytic plating process is preferablyperformed with a current density of about 20 to about 40 mA/cm² using aplating solution that includes a copper sulfate solution, a sulfuricacid solution, and a solution including chlorine ions. The selectiveelectroless plating process is preferably carried out using coppersulfate solution that includes a reducing agent such as formaldehyde orhydrazine.

Because horizontal growth of the conductive patterns 585 may be limitedin the holes, the conductive patterns 585 are vertically grown from theseed layer patterns 580 in the holes. The selective electrolytic orelectroless plating process is continuously performed until theconductive patterns 585 fill the holes and then it is continued in orderto grow the conductive patterns 585 in horizontal and verticaldirections on the mold layer 565. The conductive patterns 585 arecontinuously grown in horizontal and vertical directions indicated byarrows so that adjacent conductive patterns 585 become connected to oneanother.

The conductive patterns 585 are electrically connected to the endportions of the lower wiring 560, whereas the conductive patterns 585are separated from another portion of the lower wiring 560 due to theopening 515. That is, the conductive patterns 585 are electricallyisolated from the lower wiring 560 except for the end portions of thelower wiring 560. As a result, the method of manufacturing an inductor600 (see FIG. 13C) may be simplified and performed at lower cost byomitting an additional process involved in the formation of a contactthat electrically connects the conductive patterns 585 to the lowerwiring 560.

Referring to FIG. 13C, as the selective electrolytic or electrolessplating process proceeds, after the conductive patterns 585 verticallygrow from the seed layer patterns 580 to fill the holes, the conductivepatterns 585 grow vertically and horizontally on the mold layer 565. Asa result, a conductive line 590 having a desired width and height isformed on the mold layer 565 from the seed layer patterns 580 byconnecting the conductive patterns 585. When the conductive patterns 585are formed by the selective electroless plating process, the conductivepatterns 585 may have relatively dense structures. Particularly, theconductive patterns 585 continuously grow on the mold layer 565 in thevertical and horizontal directions so that adjacent conductive patterns585 are connected to one another on the mold layer 565. After theconductive patterns 585 grow vertically from the seed layer patterns580, they grow vertically and horizontally on mold layer 565. Theconductive line 590 is formed by the horizontal and vertical growth ofthe conductive patterns 585. The growth rate of the conductive patterns585 is preferably adjusted after the conductive patterns 585 fill theholes to form the conductive line 590 with a desired width and height onthe mold layer 565.

Referring now to FIG. 13D, after a portion of the diffusion preventionlayer 575 positioned on the mold layer 565 is removed, a protectionlayer 595 having a thickness of about 100 to 1,000 Å is formed on themold layer 565 to enclose the conductive line 590. The protection layer595 may be formed using silicon carbide or silicon nitride. Thus, theinductor 600, which has a plurality of spiral conductive lines 590, isformed on the substrate. In one embodiment of the present invention,after the mold layer 565 is removed, the protection layer 595 is formedto entirely enclose the conductive line 590.

In summary, according to the present invention, an inductor includingspiral conductive lines may be readily manufactured at a relatively lowcost by employing an electrolytic process or an electroless platingprocess.

The inductor preferably includes a conductive line having a desiredwidth and height obtained by adjusting a growth rate of conductivepatterns grown with the electrolytic plating process or the electrolessplating process.

Because the desired height of the conductive line is typically greaterthan that of a conventional inductor, the inductor may have a spiralstructure characterized by a large height on a substrate.

The manufacturing time and cost required to form the inductor may begreatly reduced because an additional process typically required toelectrically connect the inductor to a lower wiring formed on thesubstrate is omitted. The inductor may be directly formed on aconventional substrate without any additional process so that theinductor having the large height may be readily formed at low cost onthe substrate using a conventional apparatus for manufacturing aninductor.

The preferred embodiments disclosed in the drawings and thecorresponding written description are teaching examples. Those ofordinary skill in the art will understand that various changes in formand details may be made to the exemplary embodiments without departingfrom the scope of the present invention which is defined by thefollowing claims.

1. An inductor comprising: a seed layer formed on a substrate; and aconductive line formed on the seed layer, wherein the conductive line isformed by a plurality of connected conductive patterns grown from theseed layer.
 2. The inductor of claim 1, further comprising: a diffusionprevention layer formed between the substrate and the seed layer.
 3. Theinductor of claim 1, further comprising: a protection layer formed onthe conductive line.
 4. The inductor of claim 3, wherein the protectionlayer comprises silicon carbide or silicon nitride.
 5. The inductor ofclaim 3, wherein the protection layer has a thickness of about 100 to1,000 Å.
 6. The inductor of claim 1, further comprising: a mold layercomprising hole arrays respectively filled with one of the plurality ofconductive patterns.
 7. The inductor of claim 6, wherein the pluralityof conductive patterns filling the hole arrays are connected to oneanother on the mold layer to form the conductive line.
 8. The inductorof claim 6, wherein the mold layer comprises oxide or photoresist. 9.The inductor of claim 6, wherein the mold layer has a thickness of about500 to 30,000 Å.
 10. The inductor of claim 6, wherein each of the holearrays has a depth of about 500 to 30,000 Å.
 11. The inductor of claim1, further comprising: a mold layer comprising trenches respectivelyfilled with one of the plurality of conductive patterns.
 12. Theinductor of claim 11, wherein the plurality of conductive patternsfilling the trenches are connected to one another on the mold layer toform the conductive line.
 13. The inductor of claim 11, wherein the moldlayer comprises oxide or photoresist.
 14. The inductor of claim 11,wherein the mold layer has a thickness of about 500 to 30,000 Å.
 15. Theinductor of claim 11, wherein each of the trenches has a depth of about500 to 30,000 Å.
 16. The inductor of claim 1, wherein the conductiveline has a rounded upper portion.
 17. An inductor comprising: asubstrate comprising a conductive structure; a seed layer formed on thesubstrate; a mold layer formed on the seed layer, wherein the mold layerincludes hole arrays exposing the seed layer; and a conductive lineformed on the seed layer, wherein the conductive line is electricallyconnected to the conductive structure and is formed by a plurality ofconnected conductive patterns grown from the seed layer.
 18. Theinductor of claim 17, further comprising: a diffusion prevention layerformed between the substrate and the seed layer.
 19. The inductor ofclaim 17, further comprising: a protection layer formed on theconductive line.
 20. The inductor of claim 17, wherein the conductiveline has an upper portion having a mushroom shaped structure.
 21. Aninductor comprising: a substrate including a conductive structure; amold layer formed on the substrate, wherein the mold layer compriseshole arrays having inner surfaces; a seed layer formed on the innersurfaces of the hole arrays; and a conductive line formed on the seedlayer, wherein the conductive line is electrically connected to theconductive structure and is formed by a plurality of connectedconductive patterns grown from the seed layer.
 22. The inductor of claim21, further comprising: a diffusion prevention layer formed between theseed layer and the substrate including the conductive structure.
 23. Theinductor of claim 21, further comprising: a protection layer formed onthe conductive line.
 24. The inductor of claim 21, wherein theconductive line has a rounded upper portion.
 25. An inductor comprising:a substrate including a conductive structure; a mold layer formed on thesubstrate, wherein the mold layer comprises trenches having innersurfaces; a seed layer formed on the inner surfaces of the hole arrays;and a conductive line formed on the seed layer, wherein the conductiveline is electrically connected to the conductive structure and is formedby a plurality of connected conductive patterns grown from the seedlayer.
 26. The inductor of claim 25, further comprising: a diffusionprevention layer formed between the seed layer and the substrateincluding the conductive structure.
 27. The inductor of claim 25,further comprising: a protection layer formed on the conductive line.28. The inductor of claim 25, wherein the conductive line has a roundedupper portion.
 29. An inductor comprising: a substrate including aconductive structure; a mold layer formed on the substrate, wherein themold layer comprises hole arrays having inner surfaces; a first seedlayer formed on the inner surfaces of the hole arrays and on the moldlayer; a capping layer formed on the first seed layer; a second seedlayer formed on portions of the capping layer positioned in the holearrays; and, a conductive line formed on the second seed layer, whereinthe conductive line is electrically connected to the conductivestructure and is formed by a plurality of connected conductive patternsgrown from the second seed layer.
 30. The inductor of claim 29, furthercomprising: a diffusion prevention layer formed between the first seedlayer and the substrate including the conductive structure, and betweenthe first seed layer and the mold layer.
 31. The inductor of claim 29,wherein the first seed layer comprises an element selected from thegroup consisting of copper (Cu), platinum (Pt), palladium (Pd), nickel(Ni), silver (Ag), gold (Au) and any alloy thereof.
 32. The inductor ofclaim 29, wherein the capping layer comprises aluminum (Al).
 33. Theinductor of claim 32, wherein the capping layer has a thickness of about100 to 500 Å.
 34. The inductor of claim 29, wherein the second seedlayer comprises an element selected from the group consisting of copper,platinum, palladium, nickel, silver, gold and any alloy thereof.
 35. Theinductor of claim 29, further comprising a protection layer formed onthe conductive line.
 36. The inductor of claim 29, wherein theconductive line has a rounded upper portion.
 37. A method formanufacturing an inductor, comprising: forming a mold layer on a seedlayer, wherein the mold layer comprises hole arrays exposing the seedlayer; forming conductive patterns on the mold layer from the seed layerto fill the hole arrays; and forming a conductive line on the mold layerby growing the conductive patterns on the mold layer and connecting theconductive patterns.
 38. The method of claim 37, wherein forming themold layer comprises: forming a photoresist film on the seed layer; andforming a photoresist pattern on the seed layer by patterning thephotoresist film, wherein the photoresist pattern includes the holearrays that expose the seed layer.
 39. The method of claim 38, whereinforming the photoresist pattern comprises: placing a mask over thephotoresist film, the mask comprising a pattern having hole arraysarranged substantially in parallel; and, exposing the photoresist filmusing the mask.
 40. The method of claim 38, further comprising: formingan anti-reflective layer on the photoresist film.
 41. The method ofclaim 40, further comprising: removing the photoresist pattern and theanti-reflective layer after forming the conductive line.
 42. The methodof claim 41, wherein the photoresist pattern and the anti-reflectivelayer are removed using an organic stripper, a solution including ozoneat a relatively high concentration, or a standard cleaning solutionincluding carbon dioxide.
 43. The method of claim 37, wherein formingthe mold layer comprises: forming an oxide layer on the seed layer;forming a photoresist film on the oxide layer; forming a photoresistpattern on the oxide layer by patterning the photoresist film; and,forming the hole arrays through the mold layer by etching the mold layerusing the photoresist pattern as an etching mask.
 44. The method ofclaim 37, further comprising: forming a diffusion prevention layerbetween the seed layer and an underlying structure.
 45. The method ofclaim 44, further comprising: partially removing the seed layer and thediffusion prevention layer except for portions of the seed layer and thediffusion prevention layer positioned beneath the conductive line afterforming the conductive line.
 46. The method of claim 45, wherein theseed layer and the diffusion prevention layer are partially removedusing a solution including hydrogen fluoride and hydrogen peroxide orhydrogen fluoride and nitric acid.
 47. The method of claim 37, furthercomprising: forming a protection layer on the conductive line.
 48. Themethod of claim 37, wherein the conductive line is formed by anelectrolytic plating process or an electroless plating process.
 49. Themethod of claim 48, wherein the electrolytic plating process isperformed with a current density of about 20 to 40 mA/cm² using aplating solution including a copper sulfate solution, a sulfuric acidsolution and a solution including chlorine ions.
 50. A method formanufacturing an inductor, comprising: forming a mold layer on a seedlayer, wherein the mold layer comprises trenches exposing the seedlayer; forming conductive patterns on the mold layer from the seed layerto fill the trenches; and forming a conductive line on the mold layer bygrowing the conductive patterns on the mold layer and connecting theconductive patterns.
 51. The method of claim 50, wherein forming themold layer comprises: forming a photoresist film on the seed layer; andforming a photoresist pattern on the seed layer by patterning thephotoresist film, wherein the photoresist pattern includes the trenchesthat expose the seed layer.
 52. The method of claim 51, wherein formingthe photoresist pattern comprises: placing a mask over the photoresistfilm, the mask comprising a pattern having trenches substantially inparallel; and exposing the photoresist film using the mask.
 53. A methodof manufacturing an inductor comprising: forming a mold layer on asubstrate comprising a conductive structure, wherein the mold layercomprises hole arrays having inner surfaces; forming a diffusionprevention layer on the inner surfaces of the hole arrays and on themold layer; forming seed layer patterns on portions of the diffusionprevention layer positioned in the hole arrays; forming conductivepatterns from the seed layer patterns to fill the hole arrays; forming aconductive line on the mold layer by growing the conductive patterns onthe mold layer and by connecting the conductive patterns; and forming aprotection layer on the conductive line.
 54. The method of claim 53,wherein forming the seed layer patterns comprises: forming a seed layeron the diffusion prevention layer; and removing portions of the seedlayer positioned on the mold layer.
 55. The method of claim 54, whereinremoving the portions of the seed layer is performed by a chemicalmechanical polishing (CMP) process, an etch back process, or acombination of a CMP process and an etch back process.
 56. The method ofclaim 53, wherein forming the conductive line is performed by anelectrolytic plating process or an electroless plating process.
 57. Amethod of manufacturing an inductor comprising: forming a mold layer ona substrate comprising a conductive structure, wherein the mold layercomprises hole arrays having inner surfaces; forming a diffusionprevention layer on the inner surfaces of the hole arrays and on themold layer; forming a first seed layer on the diffusion preventionlayer; forming a capping layer on the first seed layer; forming secondseed layer patterns on portions of the capping layer positioned in thehole arrays; forming conductive patterns from the second seed layerpatterns to fill the hole arrays; forming a conductive line on the moldlayer by growing the conductive patterns on the mold layer and byconnecting the conductive patterns; and forming a protection layer onthe conductive line.
 58. The method of claim 57, wherein forming thesecond seed layer patterns comprises: forming a second seed layer on thecapping layer; and removing portions of the second seed layer positionedon the mold layer.